Check Static Upper Bound

Check that signal is less than (or optionally equal to) static upper bound

Library:
Simulink / Model Verification
HDL Coder / Model Verification

Description

The Check Static Upper Bound block checks if an input signal is less than (or optionally equal to) a specified lower bound at each time step and executes an assertion after comparison. The Upper bound parameter defines the upper bound. If the input signal is less than the upper bound, the assertion is true (1) and the block does nothing. If not, the block halts the simulation and returns an error message by default.

The input signal and bound can be scalars, vectors, or matrices. The input and the bound must be the same data type. The block compares the value of the input to the bound differently depending on the signal.

When comparing scalars to vectors or matrices, the block compares the scalar to each element of the non-scalar input signal or bound.
When comparing a vector or matrix signal to a vector or matrix upper bound, the block compares the input signal to the bound element-by-element.
For models with an input signal and bound that are both vectors or matrices, the input signal and bound must have the same dimensions.

Ports

Input

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`Port_1` — Input signal checked against bound
scalar | vector | matrix

Input signal checked against the upper bound specified by the Upper bound parameter.

Output

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`Port_1` — Assertion output signal
scalar

Output signal that is true (1) if the assertion succeeds and false (0) if the assertion fails. If, in the Configuration Parameters window, in the Math and Data Types section, under Advanced parameters, you select Implement logic signals as Boolean data, then the output data type is Boolean. Otherwise, the data type of the signal is double.

Dependencies

To enable this output port, select the Output assertion signal parameter check box.

Data Types: double | Boolean

Parameters

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`Upper bound` — Upper boundary value
scalar | vector | matrix

Specify the upper bound on the range of amplitudes that the input signal can have.

Command-Line Information

Parameter: max

Type: character vector

Values: scalar | vector | matrix

Default: '0'

`Inclusive boundary` — Include the upper bound in range
`on` (default) | `off`

Select this check box to make the range of valid input amplitudes include the upper bound.

Command-Line Information

Parameter: max_included

Type: character vector

Values: 'on' | 'off'

Default: 'on'

`Enable assertion` — Enable or disable check
`on` (default) | `off`

Clearing this parameter disables the block and causes the model to behave as if the block does not exist. To enable or disable all verification blocks, regardless of the setting of this option, go to the Configuration Parameters window, click Diagnostics > Data Validity, expand the Advanced parameters section, and set Model Verification block enabling to Enable all or Disable all.

Command-Line Information

Parameter: enabled

Type: character vector

Values: 'on' | 'off'

Default: 'on'

`Simulation callback when assertion fails (optional)` — Expression to evaluate when assertion fails
`''` (default) | MATLAB expression

Specify a MATLAB^® expression to evaluate when the assertion fails. Because the expression is evaluated in the MATLAB workspace, define all variables used in the expression in that workspace.

Dependencies

To enable this parameter, select the Enable assertion parameter.

Command-Line Information

Parameter: callback

Type: character vector

Values: MATLAB expression

Default: ''

`Stop simulation when assertion fails` — Whether to stop simulation when check fails
`on` (default) | `off`

Select this parameter to stop the simulation when the check fails. Clear this parameter to display a warning and continue the simulation.

Command-Line Information

Parameter: stopWhenAssertionFail

Type: character vector

Values: 'on' | 'off'

Default: 'on'

`Output assertion signal` — Create output signal
`off` (default) | `on`

Select this parameter to enable the output port.

Command-Line Information

Parameter: export

Type: character vector

Values: 'on' | 'off'

Default: 'off'

`Select icon type` — Select icon type
`graphic` (default) | `text`

Specify the style of the block icon. The graphic option displays a graphical representation of the assertion condition on the icon. The text option displays a mathematical expression that represents the assertion condition.

Command-Line Information

Parameter: icon

Type: character vector

Values: 'graphic' | 'text'

Default: 'graphic'

Model Examples

Check Signal Upper Bound with Check Static Upper Bound Block

This model uses the Check Static Upper Bound block to determine the upper bound of an input sine wave.

Open Model

View Model Verification Blocks in Verification Manager

This model contains a Signal Builder block that feeds five test signals to Model Verification blocks. The first four signals connect directly to Check Static Upper Bound blocks.

Block Characteristics

Data Types	`Boolean` \| `double` \| `enumerated` \| `fixed point` \| `half` \| `integer` \| `single`
Direct Feedthrough	`no`
Multidimensional Signals	`yes`
Variable-Size Signals	`no`
Zero-Crossing Detection	`no`

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

For information about how Simulink^® Coder™ generated code handles Model Verification blocks, see Configure Model for Debugging (Simulink Coder).

Not recommended for production code.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block checks whether each input signal element is lower than a static upper bound during simulation, but it is not included in the generated code.

Documentation

Check Static Upper Bound

Description

Ports

Input

`Port_1` — Input signal checked against bound
scalar | vector | matrix

Output

`Port_1` — Assertion output signal
scalar

Dependencies

Parameters

`Upper bound` — Upper boundary value
scalar | vector | matrix

Command-Line Information

`Inclusive boundary` — Include the upper bound in range
`on` (default) | `off`

Command-Line Information

`Enable assertion` — Enable or disable check
`on` (default) | `off`

Command-Line Information

`Simulation callback when assertion fails (optional)` — Expression to evaluate when assertion fails
`''` (default) | MATLAB expression

Dependencies

Command-Line Information

`Stop simulation when assertion fails` — Whether to stop simulation when check fails
`on` (default) | `off`

Command-Line Information

`Output assertion signal` — Create output signal
`off` (default) | `on`

Command-Line Information

`Select icon type` — Select icon type
`graphic` (default) | `text`

Command-Line Information

Model Examples

Check Signal Upper Bound with Check Static Upper Bound Block

View Model Verification Blocks in Verification Manager

Block Characteristics

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

See Also

Simulink Documentation

Support

Documentation

Check Static Upper Bound

Description

Ports

Input

Port_1 — Input signal checked against bound scalar | vector | matrix

Output

Port_1 — Assertion output signal scalar

Dependencies

Parameters

Upper bound — Upper boundary value scalar | vector | matrix

Command-Line Information

Inclusive boundary — Include the upper bound in range on (default) | off

Command-Line Information

Enable assertion — Enable or disable check on (default) | off

Command-Line Information

Simulation callback when assertion fails (optional) — Expression to evaluate when assertion fails '' (default) | MATLAB expression

Dependencies

Command-Line Information

Stop simulation when assertion fails — Whether to stop simulation when check fails on (default) | off

Command-Line Information

Output assertion signal — Create output signal off (default) | on

Command-Line Information

Select icon type — Select icon type graphic (default) | text

Command-Line Information

Model Examples

Check Signal Upper Bound with Check Static Upper Bound Block

View Model Verification Blocks in Verification Manager

Block Characteristics

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

PLC Code Generation Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion Design and simulate fixed-point systems using Fixed-Point Designer™.

See Also

Simulink Documentation

Support

`Port_1` — Input signal checked against bound
scalar | vector | matrix

`Port_1` — Assertion output signal
scalar

`Upper bound` — Upper boundary value
scalar | vector | matrix

`Inclusive boundary` — Include the upper bound in range
`on` (default) | `off`

`Enable assertion` — Enable or disable check
`on` (default) | `off`

`Simulation callback when assertion fails (optional)` — Expression to evaluate when assertion fails
`''` (default) | MATLAB expression

`Stop simulation when assertion fails` — Whether to stop simulation when check fails
`on` (default) | `off`

`Output assertion signal` — Create output signal
`off` (default) | `on`

`Select icon type` — Select icon type
`graphic` (default) | `text`

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.