Exponenta Banner

Check Static Upper Bound

Check that signal is less than (or optionally equal to) static upper bound

expand all in page
  • Library:

  • Simulink / Model Verification

    HDL Coder / Model Verification

  • Check Static Upper Bound block

Description

The Check Static Upper Bound block checks if an input signal is less than (or optionally equal to) a specified lower bound at each time step and executes an assertion after comparison. The Upper bound parameter defines the upper bound. If the input signal is less than the upper bound, the assertion is true (1) and the block does nothing. If not, the block halts the simulation and returns an error message by default.

The input signal and bound can be scalars, vectors, or matrices. The input and the bound must be the same data type. The block compares the value of the input to the bound differently depending on the signal.

  • When comparing scalars to vectors or matrices, the block compares the scalar to each element of the non-scalar input signal or bound.

  • When comparing a vector or matrix signal to a vector or matrix upper bound, the block compares the input signal to the bound element-by-element.

  • For models with an input signal and bound that are both vectors or matrices, the input signal and bound must have the same dimensions.

Ports

Input

expand all

Input signal checked against the upper bound specified by the Upper bound parameter.

Data Types: half | single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | enumerated

Output

expand all

Output signal that is true (1) if the assertion succeeds and false (0) if the assertion fails. If, in the Configuration Parameters window, in the Math and Data Types section, under Advanced parameters, you select Implement logic signals as Boolean data, then the output data type is Boolean. Otherwise, the data type of the signal is double.

Dependencies

To enable this output port, select the Output assertion signal parameter check box.

Data Types: double | Boolean

Parameters

expand all

Specify the upper bound on the range of amplitudes that the input signal can have.

Command-Line Information

Parameter: max
Type: character vector
Values: scalar | vector | matrix
Default: '0'

Select this check box to make the range of valid input amplitudes include the upper bound.

Command-Line Information

Parameter: max_included
Type: character vector
Values: 'on' | 'off'
Default: 'on'

Clearing this parameter disables the block and causes the model to behave as if the block does not exist. To enable or disable all verification blocks, regardless of the setting of this option, go to the Configuration Parameters window, click Diagnostics > Data Validity, expand the Advanced parameters section, and set Model Verification block enabling to Enable all or Disable all.

Command-Line Information

Parameter: enabled
Type: character vector
Values: 'on' | 'off'
Default: 'on'

Specify a MATLAB® expression to evaluate when the assertion fails. Because the expression is evaluated in the MATLAB workspace, define all variables used in the expression in that workspace.

Dependencies

To enable this parameter, select the Enable assertion parameter.

Command-Line Information

Parameter: callback
Type: character vector
Values: MATLAB expression
Default: ''

Select this parameter to stop the simulation when the check fails. Clear this parameter to display a warning and continue the simulation.

Command-Line Information

Parameter: stopWhenAssertionFail
Type: character vector
Values: 'on' | 'off'
Default: 'on'

Select this parameter to enable the output port.

Command-Line Information

Parameter: export
Type: character vector
Values: 'on' | 'off'
Default: 'off'

Specify the style of the block icon. The graphic option displays a graphical representation of the assertion condition on the icon. The text option displays a mathematical expression that represents the assertion condition.

Command-Line Information

Parameter: icon
Type: character vector
Values: 'graphic' | 'text'
Default: 'graphic'

Model Examples

Check Signal Upper Bound with Check Static Upper Bound Block

Check Signal Upper Bound with Check Static Upper Bound Block

This model uses the Check Static Upper Bound block to determine the upper bound of an input sine wave.

Open Model
View Model Verification Blocks in Verification Manager

View Model Verification Blocks in Verification Manager

This model contains a Signal Builder block that feeds five test signals to Model Verification blocks. The first four signals connect directly to Check Static Upper Bound blocks.

Block Characteristics

Data Types

Boolean | double | enumerated | fixed point | half | integer | single

Direct Feedthrough

no

Multidimensional Signals

yes

Variable-Size Signals

no

Zero-Crossing Detection

no

Extended Capabilities

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

See Also

| | |

Introduced before R2006a

Simulink Documentation

Support