Класс: dlhdl.Workflow
Пакет: dlhdl
Разверните заданную нейронную сеть в целевую плату FPGA
deploy программирует заданную требуемую плату с потоком битов и развертывает нейронную сеть для глубокого обучения на нем.
Примечание
Прежде чем вы запуститесь deploy функционируйте, убедитесь, что ваш хост - компьютер соединяется с платой Intel Arria 10 SoC. Для получения дополнительной информации смотрите Связь Хоста - компьютера Проверки с Советами FPGA
Разверните VGG-19 в комплект разработчика Intel® Arria® 10 SoC, который имеет single типы данных.
snet = vgg19; hTarget = dlhdl.Target('Intel'); hW = dlhdl.Workflow('Network', snet, 'Bitstream', 'arria10soc_single','Target',hTarget); hW.deploy
### Programming FPGA bitstream using JTAG ...
### Programming FPGA bitstream has completed successfully.
tableOut =
offset_name offset_address allocated_space
_______________________ ______________ _________________
"InputDataOffset" "0x00000000" "24.0 MB"
"OutputResultOffset" "0x01800000" "4.0 MB"
"SystemBufferOffset" "0x01c00000" "52.0 MB"
"InstructionDataOffset" "0x05000000" "20.0 MB"
"ConvWeightDataOffset" "0x06400000" "276.0 MB"
"FCWeightDataOffset" "0x17800000" "472.0 MB"
"EndOffset" "0x35000000" "Total: 848.0 MB"
### Loading weights to FC Processor.
### 4% finished, current time is 14-Jun-2020 18:31:07.
### 8% finished, current time is 14-Jun-2020 18:31:32.
### 12% finished, current time is 14-Jun-2020 18:31:58.
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### 20% finished, current time is 14-Jun-2020 18:32:48.
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### 44% finished, current time is 14-Jun-2020 18:35:21.
### 48% finished, current time is 14-Jun-2020 18:35:46.
### 52% finished, current time is 14-Jun-2020 18:36:11.
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### 88% finished, current time is 14-Jun-2020 18:39:58.
### 92% finished, current time is 14-Jun-2020 18:40:23.
### 96% finished, current time is 14-Jun-2020 18:40:48.
### FC Weights loaded. Current time is 14-Jun-2020 18:41:06 deploy функция начинает программировать устройство FPGA, сообщения о ходе выполнения отображений, и время, которое требуется, чтобы развернуть сеть.
Создайте файл в своей текущей рабочей директории под названием getLogoNetwork.m. Введите эти линии в файл:
function net = getLogoNetwork() data = getLogoData(); net = data.convnet; end function data = getLogoData() if ~isfile('LogoNet.mat') url = 'https://www.mathworks.com/supportfiles/gpucoder/cnn_models/logo_detection/LogoNet.mat'; websave('LogoNet.mat',url); end data = load('LogoNet.mat'); end
Используйте это изображение, чтобы запустить код:
Чтобы квантовать сеть, вам нужны продукты, перечисленные под FPGA в необходимых условиях рабочего процесса квантования.
snet = getLogoNetwork(); dlquantObj = dlquantizer(snet,'ExecutionEnvironment','FPGA'); Image = imageDatastore('heineken.png','Labels','Heineken'); dlquantObj.calibrate(Image); hTarget = dlhdl.Target('Xilinx','Interface','Ethernet'); hW = dlhdl.Workflow('Network',dlquantObj,'Bitstream','zcu102_int8','Target',hTarget); hW.deploy
### Programming FPGA Bitstream using Ethernet...
Downloading target FPGA device configuration over Ethernet to SD card ...
# Copied /tmp/hdlcoder_rd to /mnt/hdlcoder_rd
# Copying Bitstream hdlcoder_system.bit to /mnt/hdlcoder_rd
# Set Bitstream to hdlcoder_rd/hdlcoder_system.bit
# Copying Devicetree devicetree_dlhdl.dtb to /mnt/hdlcoder_rd
# Set Devicetree to hdlcoder_rd/devicetree_dlhdl.dtb
# Set up boot for Reference Design: 'AXI-Stream DDR Memory Access : 3-AXIM'
Downloading target FPGA device configuration over Ethernet to SD card done. The system will now reboot for persistent changes to take effect.
System is rebooting . . . . . .
### Programming the FPGA bitstream has been completed successfully.
offset_name offset_address allocated_space
_______________________ ______________ _________________
"InputDataOffset" "0x00000000" "48.0 MB"
"OutputResultOffset" "0x03000000" "4.0 MB"
"SystemBufferOffset" "0x03400000" "60.0 MB"
"InstructionDataOffset" "0x07000000" "8.0 MB"
"ConvWeightDataOffset" "0x07800000" "8.0 MB"
"FCWeightDataOffset" "0x08000000" "12.0 MB"
"EndOffset" "0x08c00000" "Total: 140.0 MB"
### Loading weights to FC Processor.
### FC Weights loaded. Current time is 12-Jun-2020 13:17:56calibrate | compile | dlquantizationOptions | dlquantizer | getBuildInfo | predict | validate