Check Input Resolution

Check that input signal has specified resolution

Library:
Simulink / Model Verification
HDL Coder / Model Verification

Description

The Check Input Resolution block checks whether the input signal has a specified resolution. The block input and resolution can be either a scalar or vector. The input and resolution must be the same data type.

If the Resolution parameter is a scalar, the block calculates the modulus of the input signal over the provided scalar resolution. The calculated modulus is then compared to a tolerance of 10e-3, and executes an assertion after comparison. If the modulus is less than the tolerance, the assertion is true (1) and the block does nothing. If not, the block halts the simulation and returns an error message by default. If the Resolution parameter is a vector, it asserts true (1) if the value of the input signal is equal to any of the resolution vector elements.

The block compares the input to the resolution in several additional ways depending on the dimensions of the signal and resolution.

When comparing a scalar input signal or resolution to a vector input signal or resolution, the block compares the scalar to each element of the vector.
When comparing a vector input signal to a vector resolution, the block compares the input signal to the resolution element-by-element.
For models with an input signal and resolution that are both vectors, the input signal and resolution must have the same dimensions.

Ports

Input

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`Port_1` — Input signal checked against resolution
scalar | vector

Input signal that the block checks against the resolution specified by the Resolution parameter.

Data Types: double

Output

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`Port_1` — Assertion output signal
scalar

Output signal that is true (1) if the assertion succeeds and false (0) if the assertion fails. If, in the Configuration Parameters window, in the Math and Data Types section, under Advanced parameters, you select Implement logic signals as Boolean data, then the output data type is Boolean. Otherwise, the data type of the signal is double.

Dependencies

To enable this port, select Output assertion signal.

Data Types: double | Boolean

Parameters

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`Resolution` — Resolution value to compare to input signal
scalar | vector

Specify the resolution requirement for the input signal.

Command-Line Information

Parameter: resolution

Type: character vector

Values: '1' |

real scalar or
								vector

Default: '1'

`Enable assertion` — Enable or disable check
`on` (default) | `off`

Clearing this parameter disables the block and causes the model to behave as if the block does not exist. To enable or disable all verification blocks, regardless of the setting of this option, go to the Configuration Parameters window, click Diagnostics > Data Validity, expand the Advanced parameters section, and set Model Verification block enabling to Enable all or Disable all.

Command-Line Information

Parameter: enabled

Type: character vector

Values: 'on' | 'off'

Default: 'on'

`Simulation callback when assertion fails (optional)` — Expression to evaluate when assertion fails
`''` (default) | MATLAB expression

Specify a MATLAB^® expression to evaluate when the assertion fails. Because the expression is evaluated in the MATLAB workspace, define all variables used in the expression in that workspace.

Dependencies

To enable this parameter, select the Enable assertion parameter.

Command-Line Information

Parameter: callback

Type: character vector

Values: MATLAB expression

Default: ''

`Stop simulation when assertion fails` — Whether to stop simulation when check fails
`on` (default) | `off`

Select this parameter to stop the simulation when the check fails. Clear this parameter to display a warning and continue the simulation.

Command-Line Information

Parameter: stopWhenAssertionFail

Type: character vector

Values: 'on' | 'off'

Default: 'on'

`Output assertion signal` — Create output signal
`off` (default) | `on`

Select this parameter to enable the output port.

Command-Line Information

Parameter: export

Type: character vector

Values: 'on' | 'off'

Default: 'off'

Model Examples

Check Signal Resolution with Check Input Resolution Block

This model checks the resolution of a Repeating Sequence Stair block using the Check Input Resolution block.

Open Model

Block Characteristics

Data Types	`double`
Direct Feedthrough	`no`
Multidimensional Signals	`yes`
Variable-Size Signals	`no`
Zero-Crossing Detection	`no`

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

For information about how Simulink^® Coder™ generated code handles Model Verification blocks, see Configure Model for Debugging (Simulink Coder).

Not recommended for production code.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block can be used to check whether the input signal has a specified resolution during simulation, but it is not included in the generated code.

Documentation

Check Input Resolution

Description

Ports

Input

`Port_1` — Input signal checked against resolution
scalar | vector

Output

`Port_1` — Assertion output signal
scalar

Dependencies

Parameters

`Resolution` — Resolution value to compare to input signal
scalar | vector

Command-Line Information

`Enable assertion` — Enable or disable check
`on` (default) | `off`

Command-Line Information

`Simulation callback when assertion fails (optional)` — Expression to evaluate when assertion fails
`''` (default) | MATLAB expression

Dependencies

Command-Line Information

`Stop simulation when assertion fails` — Whether to stop simulation when check fails
`on` (default) | `off`

Command-Line Information

`Output assertion signal` — Create output signal
`off` (default) | `on`

Command-Line Information

Model Examples

Check Signal Resolution with Check Input Resolution Block

Block Characteristics

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

See Also

Simulink Documentation

Support

Documentation

Check Input Resolution

Description

Ports

Input

Port_1 — Input signal checked against resolution scalar | vector

Output

Port_1 — Assertion output signal scalar

Dependencies

Parameters

Resolution — Resolution value to compare to input signal scalar | vector

Command-Line Information

Enable assertion — Enable or disable check on (default) | off

Command-Line Information

Simulation callback when assertion fails (optional) — Expression to evaluate when assertion fails '' (default) | MATLAB expression

Dependencies

Command-Line Information

Stop simulation when assertion fails — Whether to stop simulation when check fails on (default) | off

Command-Line Information

Output assertion signal — Create output signal off (default) | on

Command-Line Information

Model Examples

Check Signal Resolution with Check Input Resolution Block

Block Characteristics

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

PLC Code Generation Generate Structured Text code using Simulink® PLC Coder™.

See Also

Simulink Documentation

Support

`Port_1` — Input signal checked against resolution
scalar | vector

`Port_1` — Assertion output signal
scalar

`Resolution` — Resolution value to compare to input signal
scalar | vector

`Enable assertion` — Enable or disable check
`on` (default) | `off`

`Simulation callback when assertion fails (optional)` — Expression to evaluate when assertion fails
`''` (default) | MATLAB expression

`Stop simulation when assertion fails` — Whether to stop simulation when check fails
`on` (default) | `off`

`Output assertion signal` — Create output signal
`off` (default) | `on`

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.